In power electronics applications MOSFETs have become the devices of choice for switching high voltages and currents. When compared to bipolar devices, they have fast switching times and simple gate drive circuitry. Specifically, the double-diffusion MOSFET structure is favoured as it allows easy fabrication and self-alignment of channel length control. In such a MOSFET, current flows between transistor drain and source through a lightly doped drift region and a conduction channel that is electrically formed in the body of the transistor.
Current conduction between drain and source is electrically controlled by a voltage applied to a gate that exerts an electric field on the transistor body to form the channel. The magnitude of the gate voltage varies the channel depth and its conductivity. Application of a gate voltage may thus be used to switch the transistor between its on and off states. In its on state, the resistance from source to drain includes the resistance of the transistor's drift region. In fact, for most power MOSFETs, the drift region resistance is the dominant component of overall on-state resistance, as MOSFETs are majority carrier devices and only limited excess carriers are injected into the drift region to modulate its resistance in the MOSFET's on-state. Of course, high conductivity (and therefore low resistance) of this drift region for high current conduction is extremely desirable. Due to absence of effective modulation mechanism affecting resistance, conductivity of the drift region is mainly dependent on, and proportional to, the background doping concentration of this region.
In the MOSFET's off-state, the body region to drift region junction prevents conduction of current, provided that the potential difference across this junction does not exceed the avalanche or punch-through breakdown voltage of the junction. Almost the entire potential drop is in the drift region at drain side of this junction. The potential drop across the body region and the source region is significantly smaller than that of the drift region due to the much higher doping concentration of the body and source regions. The electric field profile in the drift region has its maximum amplitude at the junction and decreases linearly when moving away from the junction, eventually to zero. How quickly the field drops when moving away from the junction is strongly influenced by the drift region's background doping concentration. The total integrated area under the field distribution is equal to the voltage across the junction. A higher doping concentration will make the field drop more quickly, creating a higher peak junction field for the same amount of the voltage applied compared to a lower doping region.
Thus a higher doping in the drift region not only makes the on-state resistance lower but also decreases the off-state breakdown voltage of the body region to drift region junction. In conventional double diffused silicon MOSFETs, there exists a trade-off limit between the specific on-state resistance, Ron,sp and the off-state breakdown voltage, BVdss, i.e. Ron, sp∝BVdss2.5, as for example described in C. Hu, “Optimum doping profile for minimum ohmic resistance and high breakdown voltage”, IEEE Transactions on Electron Devices, Vol. ED-26(3), pp. 243-245, 1979. As such, power MOSFET designers are constantly seeking ways to lower drift region resistance without reducing the body region to drift region junction breakdown voltage.
Recently, proposed MOSFET designs alternately stack p and n layers to overcome the silicon trade-off limit, as for example illustrated in U.S. Pat. Nos. 5,216,275, 5,438,215 and European Patent EP0053854. These disclosed devices all rely on the charge compensation principle of the alternating p and n layers to increase the permissible doping of the device so that the relationship between on-state resistance and off-state breakdown voltage can be improved.
Another approach disclosed in U.S. Pat. No. 5,637,898 proposes a linearly graded doping profile to modulate the field distribution in the drift region. The width of the drift region is limited as the linear profile is achieved by the angled implantation from trenched sidewalls.
All of these proposed MOSFETS are, however, difficult to fabricate, involving expensive multi-epitaxy process, as for example detailed in G. Deboy, M. Marz, J.-P. Stengl, H. Strack, J. Tihanyi and H. Weber, “A new generation of high voltage MOSFETs breaks the limit line of silicon”, IEEE IEDM Technical Digest, pp. 683-685, 1998.
Subsequent developments have been aimed at achieving the charge compensation by other processes as for example detailed in T. Nitta, T. Minato, M. Yano, A. Uenisi, M. Harada and S. Hine, “Experimental Results and Simulation Analysis of 250V Super trench Power MOSFET (STM)”, Proc. 12th Int. Symp. Power Semiconductor Device and ICs, pp. 77-80, 2000, T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada and S. Hine, “Which is cooler, trench or Multi-Epitaxy?”, Proc. 12th International Symposium on Power Semiconductor Device and ICs, pp. 73-76, 2000, and in J. Glenn and J. Siekkinen, “A VDMOS vertical deep trench RESURF DMOS (VTR-DMOS)”, Procedure 12th International Symposium on Power Semiconductor Device and ICs, pp. 197-200, 2000. These newer processes are generally limited by the narrow window imposed by the precise charge balance needed to achieve the optimum on-resistance and the p/n layer inter-diffusion, as for example explained in P. M. Shenoy, A. Bhalla and G. M. Dolny, “Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET”, Proc. 11th International Symposium on Power Semiconductor Device and ICs, pp. 99-102, 1999.
Accordingly, there is need for an improved power MOSFET, having an improved breakdown voltage to on-state resistance relationship.